Conventionally, an imaging element that is provided with a photoreceptor element array in which pixel cells having at least a photoelectric conversion element are arranged in a two-dimensional array, and with a plurality of A/D conversion circuits that perform A/D conversion on optical signals received from the photoreceptor element array, and that is constructed as a single IC chip, and also a method of controlling this imaging element have been disclosed. High-function processing such as zoom-in functions and the like can be efficiently executed by performing A/D conversion on only the two-dimensional areas required by the imaging device, or by improving the resolution of the A/D conversion without changing the range of the voltage capable of undergoing A/D conversion. In addition, technology that achieves a miniaturization of the imaging device, as well as increases in the speed and accuracy thereof is also disclosed (see, for example, Patent document 1).
Moreover, as the A/D conversion circuit of Patent document 1, for example, the structure described in Non-patent document 1 is known. As is shown in FIG. 10, an A/D conversion circuit 20 described in Non-patent document 1 has a pulse transit circuit 1, an encoder and latch 2, a counter 3, latches 4 and 5, and a calculator 6. The functions of each of these structures are described below.
The pulse transit circuit 1 has a structure in which a single NAND circuit 101 (NAND) which serves as a startup inverter circuit that operates after receiving a pulse signal StartP in one input terminal thereof, and a plurality of inverters (INV) 102 which serve as inverter circuits are connected in a ring shape. The encoder and latch 2 encodes and holds output signals from the pulse transit circuit 1 in synchronization with a sampling signal CKs. The counter 3 counts output signals from the pulse transit circuit 1.
The latch 4 holds output signals from the counter 3 in synchronization with the sampling signal CKs. The latch 5 holds signals obtained by adding together the output signals from the encoder and latch 3 and the latch 4 in synchronization with the sampling signal CKs. The calculator 6 calculates the difference between a previous signal and a current signal using the latch 5, and outputs the result to an external latter-stage circuit. In addition, a power supply line 7A supplies power to the NAND circuit 101 and to the inverters 102 within the pulse transit circuit 1, and an input terminal 8A to which is input an analog input signal Vin which is to undergo A/D conversion is connected to this power supply line 7A.
Next, an operation of the A/D conversion circuit 20 will be described. In the pulse transit circuit 1, the pulse signal StartP is made to orbit the single NAND circuit 101 and plurality of inverters 102 which are formed in a ring shape. The number of times the pulse signal StartP orbits the pulse transit circuit 1, and also the position of the pulse signal StartP within the NAND circuit 101 and inverters 102 change in accordance with the size of the analog input signal Vin and the period of the sampling signal CKs. For example, as is shown in FIG. 11A, if the size of the analog input signal Vin increases, the propagation delay time of the NAND circuit 101 and inverters 102 becomes smaller. Because of this, the number of times the pulse signal StartP orbits the pulse transit circuit 1 increases.
The encoder and latch 2 detects the position of the pulse signal StartP within the NAND circuit 101 and inverters 102, and outputs the result as binary digital data. The counter 3 counts the number of times the pulse signal StartP has orbited the pulse transit circuit 1, and outputs the result as binary digital data. The latch 4 latches the digital data output from the counter 3. The latch 5 holds digital data obtained by adding together the digital data from the latch 4 as a high-order bit and the digital data from the encoder and latch 2 as a low-order bit. The calculator 6 calculates the difference between the digital data after it has been held in the latch 5 and the digital data before it is held in the latch 5, and outputs the result to an external latter-stage circuit.
Next, as is shown in FIG. 11B, the above-described A/D conversion circuit 20 periodically outputs digital data DT (DT1, DT2, DT3, . . . ) that corresponds to the analog input signal Vin in accordance with the period of the sampling signal CKs.
Moreover, in order to obtain more accurate imaging signals in the imaging element, it is necessary to calculate the difference between the reset level of pixel cells and the signal level of the signals accumulated during an exposure period. This is described below.
FIG. 12 is a structural view showing a pixel cell of a single pixel. As is shown in FIG. 12, a pixel cell has a photoelectric conversion element 21, a memory element 22, a first transistor 23, a second transistor 24, a third transistor 25, and a fourth transistor 26.
The functions of each of these structures are described below.
The photoelectric conversion element 21 converts a subject image into a signal charge. The memory element 22 holds the signal charges accumulated in the photoelectric conversion element 21 and converts them into voltage. The first transistor 23 transmits the signal charges accumulated in the photoelectric conversion element 21 to the memory element 22. The second transistor 24 resets the memory element 22. The third transistor 25 amplifies and then outputs the signals held in the memory element 22. The fourth transistor 26 controls the selection of pixel signals by controlling whether or not a signal amplified by the third transistor 25 is output to a common signal line 27.
Note that a source follower circuit is formed by the third transistor 25 and by a load current source (not shown) provided in the common signal line 27. In addition, the first transistor 23 is controlled by a signal (φTR) from a control circuit (not shown). The second transistor 24 is controlled by a signal (φRS) from this control circuit. The fourth transistor 26 is controlled by a signal (φSE) from this control circuit.
Next, an operation of this pixel cell will be described with reference made to FIG. 13. In the timing chart shown in FIG. 13, the level of the memory element 22 which is connected to the gate of the third transistor 25 is shown by FD, while the pixel output level which is output to the common signal line 27 is shown by Vsig.
When the control pulse φSE changes to an [H] level at a timing t1 and the fourth transistor 26 changes to ON, the output from the third transistor 25 is output to the common signal line 27. Thereafter, when the control pulse φRS changes to the [H] level at a timing t2 and the second transistor 24 changes to ON, the gates of the memory element 22 and the third transistor 25 are reset by a power supply VDD. Thereafter, when the control pulse φRS changes to the [L] level and the second transistor 24 changes to OFF, the level FD of the memory element 22 changes to a level shown by Vr′ in the graph, and the pixel output level Vsig changes to Vr. This Vr is the reset level of the pixel output.
When the control pulse φTR changes to an [H] level at a timing t3 and the first transistor 23 changes to ON, the signal charge which has been accumulated in the photoelectric conversion element 21 in accordance with the light intensity is transmitted to the memory element 22. In addition, the level FD of the memory element 22 and the pixel output level Vsig also change. Thereafter, when the control pulse φTR changes to an [L] level and the first transistor 23 changes to OFF, the level FD of the memory element 22 changes to a level shown by Vs′ in the graph, and the pixel output level Vsig changes to Vs. This Vs is the signal level of the pixel output of the signal charge accumulated in the photoelectric conversion element 21. Thereafter, when the control pulse φSE changes to an [L] level at a timing t4, the selection of the relevant pixel is ended and the pixel output to the common signal line 27 is cut off.
Here, irregularities are generated in the reset level Vr due to thermal noise and the like caused by the on-resistance of the second transistor 24. Moreover, irregularities are also generated between pixels in the reset level Vr arising from threshold value irregularities in the third transistor 25. Accordingly, all of these irregularities form noise in the reset level Vr. Because of this, noise is also generated in the signal level Vs which changes based on the reset level Vr. Accordingly, in order to detect highly accurate imaging signals from which noise has been removed, it has been necessary to detect the difference between the reset level Vr and the signal level Vs.